EDA tool : A comparative study
Before beginning with the comparative study, let us briefly understand what are EDA tools.
Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design.
EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology. Some users are foundry operators, who operate the semiconductor fabrication facilities (“fabs”) and additional individuals responsible for utilizing the technology design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs or field-programmable gate arrays, customizable integrated circuit designs.
Digital design flow regardless of technology is a fully automated process. Design flow consists of several steps and there is a need for a toolset in each step of the process. Modern FPGA/ASIC projects require a complete set of CAD (Computer Aided Design) design tools.
Followings are the most common tools available in the market that are briefly explained here:
- Design Capture Tools:- Design entry tool encapsulates a circuit description. These tools capture a design and prepare it for simulation. Design requirements dictate type of the design capture tool as well as the options needed. Some of the options would be: Manual netlist entry, Schematic capture, Hardware Description Language (HDL) capture (VHDL, Verilog), State diagram entry
- Simulation and Verification Tools:- Functional verification tool confirms that the functionality of a model of a circuit conforms to the intended or specified behavior, by simulation or by formal verification methods. These tools are must have tools. There are two major tool sets for simulation: Functional (Logic) simulation tools and Timing simulation tools. Functional simulators verify the logical behavior of a design based on design entry. The design primitives used in this stage must be characterized completely. Timing simulators on the other hand perform timing verifications at multiple stages of the design. In this simulation the real behavior of the system is verified when encountering the circuit delays and circuit elements in actual device. In general, the simulation information reflects the actual length of the device interconnects. This information is “back annotated” to the corresponding design entry for final logic simulation. That is why this process of simulation sometimes is called “back annotation simulation”.
- Layout Tools:- ASIC designers usually use these tools. Designers transform a logic representation of an ASIC into a physical representation that allows the ASIC to be manufactured. The transistor layout tools take a cell level ASIC representation and for a given technology create a set of layers representing transistors for each cell. Physical design tool works in conjunction with floor planning tools that show where various cells should go on the ASIC die.
- Synthesis and Optimization Tools:- Synthesis tools translate abstract descriptions of functionality such as HDL into optimal physical realizations, creating netlists that can be passed to a place and route tool. Then, the designer maps the gate level description or netlist to the target design library and optimizes for speed, area or power consumption.
Now, let us see a descriptive study of various tools:
DRC (Design Rule Checking):- Electronic design automation is used extensively to ensure that designers do not violate design rules; a process called design rule checking (DRC). DRC is a major step during physical verification signoff on the design, which also involves LVS (layout versus schematic) checks, XOR checks, ERC (electrical rule check), and antenna checks. The importance of design rules and DRC is greatest for ICs, which have micro- or nano-scale geometries; for advanced processes, some fabrications also insist upon the use of more restricted rules to improve yield.
The main objective of design rule checking (DRC) is to achieve a high overall yield and reliability for the design. If design rules are violated the design may not be functional. To meet this goal of improving die yields, DRC has evolved from simple measurement and Boolean checks, to more involved rules that modify existing features, insert new features, and check the entire design for process limitations such as layer density. A completed layout consists not only of the geometric representation of the design, but also data that provides support for the manufacture of the design.
DRC software usually takes as input a layout in the GDSII standard format and a list of rules specific to the semiconductor process chosen for fabrication. From these it produces a report of design rule violations that the designer may or may not choose to correct.
DRC products define rules in a language to describe the operations needed to be performed in DRC. For example, Mentor Graphics uses Standard Verification Rule Format (SVRF) language in their DRC rules files and Magma Design Automation is using Tcl-based language.
DRC is a very computationally intensive task. Usually DRC checks will be run on each sub-section of the ASIC to minimize the number of errors that are detected at the top level.
More on DRC by Aniket Kesarkar — https://aniket-kesarkar18.medium.com/eda-tools-4c9285f6072f
LVS(layout versus schematic):- A successful design rule check (DRC) ensures that the layout conforms to the rules designed/required for faultless fabrication. However, it does not guarantee if it really represents the circuit you desire to fabricate. This is where an LVS check is used.
The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.
LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, as well as the connections between them. This netlist is compared by the “LVS” software against a similar schematic or circuit diagram’s netlist.
Spice:- SPICE (“Simulation Program with Integrated Circuit Emphasis”)] is a general-purpose, open-source analog electronic circuit simulator. It is a program used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior.
SPICE became popular because it contained the analyses and models needed to design integrated circuits of the time, and was robust enough and fast enough to be practical to use. Precursors to SPICE often had a single purpose: The BIAS program, for example, did simulation of bipolar transistor circuit operating points; the SLIC program did only small-signal analyses. SPICE combined operating point solutions, transient analysis, and various small-signal analyses with the circuit elements and device models needed to successfully simulate many circuits.
More on spice by Kshitij Kadam — https://kshitij-kadam.medium.com/lucubrate-through-eda-tools-7c21560e8354
HDL works:- HDL Works is a supplier of front-end VHDL / Verilog design tools, translators and an FPGA / PCB pin assignment verification tool. HDL Works has over 15 years experience developing HDL tools. All tools are available on Windows and Linux operating systems.
Combines block diagrams, state diagrams, truth tables and HDL code. It will give you a complete overview of any VHDL or Verilog design in seconds. Features include verification, linting and HTML generation.
When using large FPGA’s on a PCB making sure that the FPGA pins are connected to the right signals is a cumbersome task.
IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment. A text editor focused at VHDL and Verilog, using a Multiple Document Interface. (Free of charge)
Electric:- Electric is an EDA tool used to draw schematics and to make integrated circuit (IC) layouts. It can also handle hardware description languages like VHSIC Hardware Description Language and Verilog. Throw in the various analyses options and synthesis categories, and you have a complete VLSI design package. Let us now take a glimpse into the many features of this design system.
You do not need to look at your tool’s resources first, before planning your design. Most of the components you might need — be it different technologies or multiple file formats — come ready with this software package. To help you ease in, each technology comes with a description of all characteristics of its components and wires including graphical details, design rules and simulation aspects. You just have to add in the technology module to the specific environment and use the technology editor to find your way around.
Simulink:- Simulink is a MATLAB-based graphical programming environment for modeling, simulating and analyzing multidomain dynamical systems. Its primary interface is a graphical block diagramming tool and a customizable set of block libraries. It offers tight integration with the rest of the MATLAB environment and can either drive MATLAB or be scripted from it. Simulink is widely used in automatic control and digital signal processing for multidomain simulation and model-based design.
in addition, MathWorks and other third-party hardware and software products can be used with Simulink. For example, Stateflow extends Simulink with a design environment for developing state machines and flow charts.
MathWorks claims that, coupled with another of their products, Simulink can automatically generate C source code for real-time implementation of systems. As the efficiency and flexibility of the code improves, this is becoming more widely adopted for production systems, in addition to being a tool for embedded system design work because of its flexibility and capacity for quick iteration. Embedded Coder creates code efficient enough for use in embedded systems.
More on Simulink and Electric by Shripad Kulkarni- https://medium.com/@shripad.kulkarni18/eda-tools-simulink-electric-183730002c55
Below are a list of various software that you can check out!
Commercial software
- Assura, Dracula and PVS by Cadence Design Systems
- Calibre by Mentor Graphics
- Guardian LVS by Silvaco
- Quartz LVS by Magma Design Automation
- IC Validator by Synopsys
- PowerLVS by Polyteda LLC|POLYTEDA LLC
- VERI and HVERI by Zeni EDA
Free software
- KLayout https://klayout.de/
- Magic http://opencircuitdesign.com/magic/
References:-